1. Technical Field
This invention relates to a data processing apparatus.
2. Related Art
Reconfigurable circuits (also called programmable logical circuits) of a PLD (Programmable Logic Device), an FPGA (Field Programmable Gate Array), etc., whose internal logical circuit configurations can be reconfigured (changed) become widespread. In general PLD and FPGA, when the circuit is started, the internal logical circuit configuration is set; PLD and FPGA whose logical circuit configurations can be changed during the operation of the circuits are also developed. Use of a DRP (Dynamic Reconfigurable Processor) whose internal logical circuit configurations can be dynamically reconfigured proceeds.
A tool for automatically converting a program to be implemented describing processing to be implemented in a language of C++, etc., into a circuit or a time-series pipeline of circuits configured on a reconfigurable circuit, namely, generating circuit information representing such a circuit or a pipeline is also devised.
Processing to be executed by the reconfigurable circuit contains processing wherein one processing (called postprocessing) synchronously inputs the results of a plurality of types of different processing (preprocessing) executed before the processing. There is a case where the plurality of types of preprocessing perform output having asynchronous relationship. The case where the different types of processing perform output having asynchronous relationship is, for example, a case where since a loop does not exist in different processing although a loop exists in one processing, if the same input data is given to both, a different delay occurs until the processing result is obtained from input between the former and the latter. When processing in which a loop exists and processing in which no loop exists advances processing in accordance with a clock, processing in which a loop exists delays as much as the loop and thus such a delay difference occurs. Thus, when a circuit for executing such processing is reconfigured on a reconfigurable circuit, a mechanism for synchronizing the processing results of the circuits of the preprocessing with each other and giving the results to the postprocessing.